1. Technical Field
The present invention relates to a voltage divider and a PLL having a voltage divider, and more particularly, to a voltage divider having a varied output level depending on an operating frequency.
2. Description
A phase lock loop (PLL) circuit is generally regarded as a basic component of conventional electronic systems, used as a frequency feedback circuit to generate an optional frequency synchronizing to a frequency of an externally input signal or as a synchronization circuit to synchronize a clock signal applied to each circuit block.
The PLL circuit has been widely used in communication, multimedia and other applications, such as a frequency synthesizing circuit, a clock recovery circuit of a data processing circuit, an FM demodulator, a MODEM, tone decoder, etc., for example.
FIG. 1 is a block diagram illustrating an example of a conventional PLL circuit. As shown in FIG. 1, a general PLL circuit 10 includes a phase-frequency detector (PFD) 12, charge pump (CP) 14, loop filter (LF) 16 and voltage controlled oscillator (VCO) 18.
The PLL circuit 10 outputs a clock having the same frequency and phase as those of an external reference clock Ext. The PLL circuit 10 may further include a divider DIV (not shown) for dividing an output of the VCO 18 and applying the divided output to the PFD 12. The divider DIV may be further adapted when a frequency higher than the external clock Ext is needed.
An example of the PLL circuit 10 without the divider DIV is described as follows. The PFD 12 compares frequency and phase of the external reference clock Ext and an internal clock Int, which is an output of the VCO 18. The PFD 12 outputs an up signal UP or down signal DN.
The up signal UP is provided so that an oscillation clock of the VCO 18 becomes relatively faster when the internal clock Int is slower than the external reference clock Ext. The down signal DN is provided so that the VCO 18 oscillates relatively more slowly when the internal clock Int is faster than the external reference clock Ext.
The CP 14 controls an output charge amount in response to the up or down signal UP or DN from the PFD 12. As is known, in the CP 14, an output charge amount may increase by the up signal UP and may decrease by the down signal DN. According to this operation of the CP 14, the LP 16 generates a control voltage VCTRL by performing low pass filtering of an output of the CP 14.
The VCO 18 generates the internal clock Int as the oscillation signal having a given frequency based on the control voltage VCTRL generated by the LF 16. The VCO 18 outputs the internal clock Int having a high frequency or a low frequency, according to the control voltage VCTRL.
As a result, the up signal UP is used to increase the control voltage VCTRL of the VCO 18, passing through the CP 14 and the LF 16, and thus the VCO 18 outputs the clock Int at a higher frequency, as compared with the previous output of the VCO 18. In contrast, the down signal DN is used to decrease the control voltage VCTRL of the VCO 18, passing through the CP 14 and the LF 16, so that the VCO 18 oscillates the internal clock Int at a relatively lower frequency.
The conventional PLL circuit 10 described above is a feedback circuit, and therefore requires a relatively large amount of time for performing an initial step through a stabilized step. That is, in operation of the overall system, an operating time of the PLL circuit 10 has a relatively high ratio and thus may significantly affect operation of the overall system.
In the PLL circuit 10, repeated operation of the PFD 12, CP 14, LF 16 and VCO 18 is performed hundreds or thousands of times, and frequency and phase of the reference clock Ext and the internal clock Int become equal. Then, the overall circuit can maintain a stabilized state. The time taken to obtain the stabilized state of the overall PLL circuit 10 is called a lock-in time, which is needed in all kinds of PLL circuits. The lock-in time occupies much of the operating time of the PLL circuit 10, and thus the overall operating time of the PLL circuit 10 can be reduced by lessening the lock-in time.
However, when a PLL circuit is designed to rapidly correspond to a changed level of the reference clock Ext and the internal clock Int to reduce the lock-in time, the PLL circuit in the stabilized state is varied by external noise or fluctuation. Therefore, the overall PLL circuit becomes unstable. That is, it deviates from a basic principle of PLL circuit design, which is that when phase and frequency are first fixed, the PLL circuit must continuously maintain the stable state. It is desirable to maintain stability in the basic form of a general PLL circuit and simultaneously to reduce the lock-in time.